In various systems, data is delivered with high reliability over a bus, or stored in memory. In such systems, it is typically sufficient to protect the data using coding schemes that provide single error correction (SEC) and double error detection (DED) capabilities. SEC-DED coding schemes are known in the art. For example, U.S. Pat. No. 7,530,008, whose disclosure is incorporated herein by reference, describes an encode circuit that is coupled to receive input data and is configured to generate corresponding code words, and a decode circuit that is coupled to receive code words and is configured to detect an error in the code words (and may, in some cases, correct the error.) Each code word comprises a plurality of b-bit portions (b is an integer greater than one). Additionally, each code word comprises a first set of b check bits used to detect a magnitude of an error in a b-bit portion of the plurality of b-bit portions. Each code word further comprises a second set of w check bits used to locate which one of the plurality of b-bit portions is the b-bit portion containing the error (w is an integer greater than zero and less than b).
U.S. Pat. No. 6,041,430, whose disclosure is incorporated herein by reference, describes a method and an apparatus for detecting and correcting single bit errors, detecting double bit errors, and detecting multiple bit errors within a nibble of a data field comprising 135 data bits and 9 check bits. The 9 check bits are generated based on the 135 data bits. The 9 check bits are appended to the data bits and the cumulative data field is checked for errors. An error detection syndrome is generated that indicates whether an error has occurred and whether the error is correctable. Check bit generation and error detection syndrome generation is accomplished based on the ordering in an ECC code matrix.
U.S. Pat. No. 7,447,948, whose disclosure is incorporated herein by reference, describes methods and an apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single error detection (SED) operation that allows state machines to be stopped within a single cycle when an error is detected, and enables a corresponding single error correction (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.